In association with an increase in communication traffic, construction of a large-capacity optical network using wavelength division multiplexing (WDM) is being pursued. Application of a planer lightwave circuit (PLC) which can be mass-manufactured is promising for miniaturization and cost-reduction of a WDM optical transmission system.
FIGS. 4(a) to 4(e) are views showing processes for manufacturing a quartz-based planer lightwave circuit device 100 which is taken as a conventionally-used PLC-type integrated element. When the planer lightwave device 100 is manufactured through the processes shown in FIGS. 4(a) to 4(e), silicon glass is deposited on a substrate 110 to form a lower cladding layer 120 and a core layer 130 through use of a flame hydrolysis deposition (FHD) technique or a chemical vapor deposition (CVD) technique [formation of a film on a lower plate; see FIG. 4(a)].
Next, photoresists 151, 152 constituting a lightwave pattern are formed on the deposited core layer 130 as a mask to be used in the next process of reactive ion etching (RIE) [see FIG. 4(b)]. A monolayer mask—which has a thickness of 5 μm and contains, e.g., novolak, as the principal ingredient—can be used for the photoresists.
Specifically, the device having such photoresists patterned thereon is processed by means of dry etching in a CF-based gas through use of the RIE process, whereby unwanted areas other than the masked areas are removed to thus form waveguide cores 131, 132 [processing of cores using the RIE process; see FIG. 4(c)]. Subsequently, the photoresists 151, 152 are removed by means of a technique, such as rinsing with an organic solvent or ashing [see FIG. 4(d)].
Further, silicon glass is deposited on the device in which the waveguide cores 131, 132 are formed through the RIE process and from which the photoresists 151, 152 are removed, thereby forming an upper cladding layer 140 [see FIG. 4(e)]. In order to achieve a thermal insulation effect or a light shielding effect when the dry etching is performed through the RIE process, a portion of the cladding layer 120 and a portion of the core layer 131, 132 are sometimes etched to the surface of the substrate 110 or to any point before reaching the surface of the substrate 110.
In addition to using the photoresists 151, 152 shown in FIG. 4, a conceivable mask to be used for dry etching at the time of formation of the waveguide cores includes a two-layer mask formed from a layer or a photoresist layer, the layer being formed from a high heat-resistant resin or metal, such as chromium, through processes shown in FIGS. 5(a) to 5(c).
Specifically, as shown in FIG. 5(a), a layer 160—which is formed from highly heat-resistant resin such as polyimide, or metal such as chromium or copper, and which is to become a lower layer mask—is formed on the overall core layer 130 of the substrate 110 having the lower cladding layer 120 and the core layer 130 formed therein. Next, photoresists 171, 172 constituting the waveguide core pattern are formed on the layer 160 by means of photolithography.
As shown in FIG. 5(b), the substrate is then subjected to etching through the RIE process, thereby forming lower masks 161, 162 constituting the waveguide core pattern. At this time, when the layer is formed from heat-resistant resin, an oxygen gas is used. When the layer 160 is formed from metal, etching is performed through use of a chlorine gas.
When the two-layer masks 151, 152, 161, and 162 are formed from the lower masks 161, 162 and the upper photoresist 170, the substrate is then etched through the RIE process through use of the CF-based gas, thereby forming the waveguide cores 131, 132 [see FIG. 5(c)]. Japanese Patent Laid-Open No. HEI 10-142438 describes an embodiment where copper is used as the lower mask shown in FIG. 5(b).
However, in the device manufacturing method shown in FIGS. 4(a) to 4(e), the photoresists used as the mask during the RIE process are thermally deformed by the heat developing in the substrate 110 during dry etching of silicon glass. Hence, there still arises a problem of occurrence of variations in the accuracy of formation of the waveguide core, which is caused as a result of deformation of the pattern serving as the mask.
Put another way, according to the technique shown in FIGS. 4(a) to 4(e), the width of the photoresists becomes reduced by the heat developing in the substrate 110 during the RIE processes, whereby an upper portion of the side surface of the core is sloped, thereby posing difficulty in accurately, stably forming the shape of the waveguide core.
Specifically, prevention of accuracy deterioration due to thermal deformation of the mask and lessening of variations in the width of the core are indispensable for a silicon glass etching process using etching such as the RIE process. Particularly, when an arrayed waveguide grating (AWG) is manufactured through the RIE process, difficulty may sometimes be encountered in providing an accurate difference in optical path lengths required to branch and merge the light beams spaced by a specified wavelength.
Against the backdrop of cost-reduction and high integration of the PLC being required with an aim of high-speed, large-capacity communication, a highly-integrated PLC device can be embodied through use of a structure (a high Δ structure) where a large difference exists between the specific refractive index of the core and the specific refractive index of the PLC device. However, this high Δ structure requires a reduction in the width of the core, and hence variations in processing of the light waveguide such as those mentioned previously must be reduced.
To this end, another conceivable way to improve the accuracy of formation of the waveguide core is use, as the mask for use in the RIE process, the two-layer mask where the photoresists 171, 172 are provided on the layers 161, 162 of high heat-resistant resin, such as polyimide, or metal.
However, this technique also requires another RIE process for patterning the lower layers 161, 162, which poses difficulty in curtailing costs. Moreover, since the number of processes is large, process errors arising the RIE process of the lower mask are accumulated to a greater extent as compared with the case of a monolayer mask, thereby increasing variations in processing.
Specifically, variations in the thickness of the lower masks 161, 162, variations in a rate at which the lower masks 161, 162 are etched, and variations in lateral etching of the mask layers are accumulated by means of RIE of the lower masks 161, 162.
The present invention has been conceived in view of such a problem and provides a device manufacturing method which renders etching accuracy high and curtails manufacturing costs when a device is manufactured in association with etching, such as RIE, where a device which is an object of etching evolves heat.